SolidVer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When Experience Counts

 

 

 

 

 

 

 

 

 

 

 

 

 

Home

About Us

Expertise

Services

Careers

Contact Us

 

 

 

 

 

 

 

 

 

 

 

 

          Services

 

 

 

 

 

 

 

 

·       Verification solutions

 

Consulting for the right verification solution based on schedule complexity, budget and resources.

 

Time to market, verification

solutions, for complex

ASICs projects.

 

 

 

Suggest a number of creative verification solutions for the

same ASIC design.

 

 

 

 

·       Verification tools

 

 

Selecting the right verification tools and methodologies.

 

 

 

 

·       Design Verification

                    Architecture and

                    Methodology               

·       Design robust structured verification architecture.

·       Flexible for design changes.

·       Enable fast integration for full chip and system levels.

·       Design generic verification environments, for reuse.

 

 

 

 

·       Review existing ASIC

                    designs architecture

 

Some of our customers developed their ASICs on a very short

schedule with many design changes and the reviews we did were found to be very useful.

 

 

 

 

·       Test plans

 

Prepare test plans specification.

 

 

 

 

·       Verification    

                    environments  

 

Code the verification environments, including the reference model, generators, drivers, monitors, bus functional model (BFM), checkers and coverage.

 

 

 

 

·       Reviewing existing

                    projects

Reviewing existing verification environments, generation and coverage, in order to find uncovered features.

 

 

 

 

·       ASIC Model  Checking

Coding ASIC models, including coding the input generators

and behavioral models.

 

 

 

 

·       Functional Coverage  

Define and implement functional coverage for existing projects.

 

 

 

 

·       Fast ramp Up              

Based on our experience, it's possible to plan the verification tasks in a way that will enable start finding real ASICs bugs in a very short schedule.

 

 

 

 

 

 

 

 

 

 

 

© SolidVer,. All rights reserved.